AT45DB641E datasheet(34/72 Pages) ETC2

34 / 72 page

AT45DB641E

DS-45DB641E-027E–DFLASH–1/2014

10.2.1 Exit Ultra-Deep Power-Down

To exit from the Ultra-Deep Power-Down mode, the CS pin must simply be pulsed by asserting the CS pin, waiting the

minimum necessary t

CSLU time, and then deasserting the CS pin again. To facilitate simple software development, a

dummy byte opcode can also be entered while the CS pin is being pulsed just as in a normal operation like the Program

Suspend operation; the dummy byte opcode is simply ignored by the device in this case. After the CS pin has been

deasserted, the device will exit from the Ultra-Deep Power-Down mode and return to the standby mode within a

maximum time of t

XUDPD. If the CS pin is reasserted before the tXUDPD time has elapsed in an attempt to start a new

operation, then that operation will be ignored and nothing will be performed. The system must wait for the device to return

to the standby mode before normal command operations such as Continuous Array Read can be resumed.

Since the contents of the SRAM buffers cannot be maintained while in the Ultra-Deep Power-Down mode, the SRAM

buffers will contain undefined data when the device returns to the standby mode.

Figure 10-4. Exit Ultra-Deep Power-Down

Chip Select Low

By asserting the CS pin, waiting the minimum necessary tXUDPD time, and then clocking in the first bit of the next

Opcode command cycle. If the first bit of the next command is clocked in before the tXUDPD time has elapsed, the

device will exit Ultra Deep Power Down, however the intended operation will be ignored.

Figure 10-5. Exit Ultra-Deep Power-Down (Chip Select Low)

ICC

High-impedance

Ultra-Deep Power-Down Mode Current

Active Current

Standby Mode Current

tXUDPD

tCSLU

AT45DB641E Datasheet(PDF) 34 Page - List of Unclassifed Manufacturers