ADC12DL080 datasheet(21/35 Pages) TI1

21 / 35 page

ADC12DL080

www.ti.com

SNAS345 – FEBRUARY 2006

Typical Performance Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =

+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Units for SNR

and SINAD are dBFS. Units for SFDR and Distortion are dBc. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ

= 25°C

tOD vs. VDR, VA = VD = 3.6V

Spectral Response @ 20 MHz Input

Spectral Response @ 39 MHz Input

Spectral Response @ 200 MHz Input

Intermodulation Distortion, fIN1= 19.6 MHz, fIN2 = 20.2 MHz

Power Consumtion vs. fCLK

Functional Description

Operating on a single +3.3V supply, the ADC12DL080 uses a pipeline architecture and has error correction

circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The

user has the choice of using an internal 1.0 Volt or an external reference. Any external reference is buffered on-

chip to ease the task of driving that pin.

The output word rate is the same as the clock frequency, which can be between 10 MSPS and 80 MSPS

(typical) with fully specified performance at 80 MSPS. The analog input for both channels is acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle

stabilization and output data format are selectable. The output data format can be set for offset binary or two's

complement.

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ADC12DL080 Datasheet(PDF) 21 Page - Texas Instruments