ADS1113 datasheet(18/38 Pages) TI1

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ADS1113

ADS1114

ADS1115

SBAS444B – MAY 2009 – REVISED OCTOBER 2009

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When reading from the ADS1113/4/5, the previous

POINTER REGISTER

value written to the Pointer register determines the

The four registers are accessed by writing to the

Pointer register byte; see Figure 30. Table 6 and

read, a new value must be written to the Pointer

Table 7 indicate the Pointer register byte map.

the master issues a slave address byte with the R/W

Table 6. Register Address

bit low, followed by the Pointer register byte. No

BIT 1

BIT 0

additional data need to be transmitted, and a STOP

condition can be issued by the master. The master

Conversion register

may now issue a START condition and send the

Config register

slave address byte with the R/W bit high to begin the

Lo_thresh register

read. Table 10 details this sequence. If repeated

Hi_thresh register

reads from the same register are desired, there is no

need to continually send Pointer register bytes,

because the ADS1113/4/5 store the value of the

CONVERSION REGISTER

Pointer register until it is modified by a write

The 16-bit register contains the result of the last

operation. However, every write operation requires

conversion

binary

twos

complement

format.

the Pointer register to be written.

Following reset or power-up, the Conversion register

is cleared to '0', and remains '0' until the first

REGISTERS

conversion is completed.

The ADS1113/4/5 have four registers that are

The register format is shown in Table 8.

accessible via the I2C port. The Conversion register

contains the result of the last conversion. The Config

CONFIG REGISTER

operating modes and query the status of the devices.

The 16-bit register can be used to control the

Two registers, Lo_thresh and Hi_thresh, set the

ADS1113/4/5 operating mode, input selection, data

threshold values used for the comparator function.

rate, PGA settings, and comparator modes. The

Table 7. Pointer Register Byte (Write-Only)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Table 8. Conversion Register (Read-Only)

BIT

NAME

D15

D14

D13

D12

D11

D10

Table 9. Config Register (Read/Write)

BIT

NAME

MUX2

MUX1

MUX0

PGA2

PGA1

PGA0

MODE

blank

BIT

NAME

DR2

DR1

DR0

COMP_MODE

COMP_POL COMP_LAT

COMP_QUE1

COMP_QUE0

Default = 8583h.

Bit [15]

OS: Operational status/single-shot conversion start

This bit determines the operational status of the device.

This bit can only be written when in power-down mode.

For a write status:

0 : No effect

1 : Begin a single conversion (when in power-down mode)

For a read status:

0 : Device is currently performing a conversion

1 : Device is not currently performing a conversion

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