VDD

LI

HI

VDD

HS

HB

HOH

HOL

HS

LOH

LOL

VSS

A

B

C

D

1

2

3

4

Top View

VDD

LI

HI

VDD

HS

HB

HOH

HOL

HS

LOH

LOL

VSS

A

B

C

D

1

2

3

4

Bump Side

LM5113

www.ti.com

SNVS725E – JUNE 2011 – REVISED JANUARY 2012

Figure 2. micro SMD

Table 2. Pin Descriptions

Pin Number

Name

Description

Applications Information

micro SMD

LLP-10

1

VDD

5V Positive gate drive supply

Locally decouple to VSS using low ESR/ESL

capacitor located as close to the IC as possible.

D3

2

HB

High-side gate driver bootstrap

Connect the positive terminal of the bootstrap

rail

capacitor to HB and the negative terminal to HS.

The bootstrap capacitor should be placed as

close to the IC as possible.

D2

3

HOH

High-side gate driver turn-on

Connect to the gate of high-side GaN FET with a

output

short, low inductance path. A gate resistor can be

used to adjust the turn-on speed.

D1

4

HOL

High-side gate driver turn-off

Connect to the gate of high-side GaN FET with a

output

short, low inductance path. A gate resistor can be

used to adjust the turn-off speed.

5

HS

High-side GaN FET source

Connect to the bootstrap capacitor negative

connection

terminal and the source of the high-side GaN

FET.

B4

6

HI

High-side driver control input

The LM5113 inputs have TTL type thresholds.

Unused inputs should be tied to ground and not

left open.

A4

7

LI

Low-side driver control input

The LM5113 inputs have TTL type thresholds.

Unused inputs should be tied to ground and not

left open.

A2

8

VSS

Ground return

All signals are referenced to this ground.

A1

9

LOL

Low-side gate driver sink-current

Connect to the gate of the low-side GaN FET with

output

a short, low inductance path. A gate resistor can

be used to adjust the turn-off speed.

B1

10

LOH

Low-side gate driver source-

Connect to the gate of high-side GaN FET with a

current output

short, low inductance path. A gate resistor can be

used to adjust the turn-on speed.

EP

Exposed Pad

It is recommended that the exposed pad on the

bottom of the package be soldered to ground

plane on the PC board to aid thermal dissipation.

(1)

A3 and C4, C1 and D4 are internally connected.

(2)

A3 and C4, C1 and D4 are internally connected.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2011–2012, Texas Instruments Incorporated

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