LM5000

SNVS176D – MAY 2004 – REVISED MARCH 2007

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Figure 4. 700 kHz operation, 48V output

Block Diagram

Boost Regulator Operation

The LM5000 utilizes a PWM control scheme to regulate the output voltage over all load conditions. The operation

can best be understood referring to the block diagram and Figure 5. At the start of each cycle, the oscillator sets

the driver logic and turns on the NMOS power device conducting current through the inductor, cycle 1 of Figure 5

(a). During this cycle, the voltage at the COMP pin controls the peak inductor current. The COMP voltage will

increase with larger loads and decrease with smaller. This voltage is compared with the summation of the SW

volatge and the ramp compensation.The ramp compensation is used in PWM architectures to eliminate the sub-

harmonic oscillations that occur during duty cycles greater than 50%. Once the summation of the ramp

compensation and switch voltage equals the COMP voltage, the PWM comparator resets the driver logic turning

off the NMOS power device. The inductor current then flows through the output diode to the load and output

capacitor, cycle 2 of Figure 5 (b). The NMOS power device is then set by the oscillator at the end of the period

and current flows through the inductor once again.

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