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LM5000 Datasheet(PDF) 12 Page - Texas Instruments

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Part # LM5000
Description  High Voltage Switch Mode Regulator
PDF  23 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LM5000 Datasheet(HTML) 12 Page - Texas Instruments

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fPC2 =
1
2SCC2(RC //RO)
(in Hz)
fZC =
1
2SCCRC
(in Hz)
fPC =
1
2S(RC + RO)CC
(in Hz)
(in Hz)
RHPzero =
VOUT(D')
2
2S,LOADL
LM5000
SNVS176D – MAY 2004 – REVISED MARCH 2007
www.ti.com
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be
designed to have a bandwidth of ½ the frequency of the RHP zero or less. This zero occurs at a frequency of:
(10)
where ILOAD is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in
the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to
Compensation section to set this pole in the area of 10Hz to 100Hz. The frequency of the pole created is
determined by the equation:
(11)
where RO is the output impedance of the error amplifier, 850kΩ. Since RC is generally much less than RO, it does
not have much effect on the above equation and can be neglected until a value is chosen to set the zero fZC. fZC
is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with
different load currents as shown by the equation, so setting the zero is not exact. Determine the range of fP1 over
the expected loads and then set the zero fZC to a point approximately in the middle. The frequency of this zero is
determined by:
(12)
Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to
100Hz range, change each value slightly if needed to ensure both component values are in the recommended
range. After checking the design at the end of this section, these values can be changed a little more to optimize
performance if desired. This is best done in the lab on a bench, checking the load step response with different
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should
produce a stable, high performance circuit. For improved transient response, higher values of RC (within the
range of values) should be chosen. This will improve the overall bandwidth which makes the regulator respond
more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more
in depth discussion of compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of
RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole
follows:
(13)
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,
fPC2 must be greater than 10fPC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP
zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the
crossover visually by placing a
−20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is
at less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also
be improved some by adding CC2 as discussed earlier in the section. The equation for ADC is given below with
additional equations required for the calculation:
12
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Links: LM5000



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