1

2

3

4

13

14

15

16

SW2

PGND2

FB2

EN2

EN1

nPOR2

5

12

SGND

nPOR1

6

7

8

10

11

9

PGND1

SW1

FB1

SDA

SCL

nPOR2

nPOR1

AND

AND

OR2

PGND

SW

Buck1

FB1

EN_I2C

EN1

SW1

PGND1

PGND

SW2

Buck2

POR2

FB2

EN2

SW2

PGND2

SGND

buck2 control

buck1 control

FB1

SDA

SCL

I

2

C

Registers

EPROM

EN2

FB2

SCL

SDA

EN1

POR1

EN_bk2

EN_bk1

U1

U2

LM3370

www.ti.com

SNVS406M – NOVEMBER 2005 – REVISED AUGUST 2011

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Diagram

LLP CONNECTION DIAGRAM AND PACKAGE MARKING INFORMATION

•

The physical placement of the package marking will vary from part to part.

•

Date Code - UZXYTT format. ’U’ - Wafer fab code; ’Z’ - assembly site code; ’XY’ 2 digit date code; ’TT’ die

run code

•

See National Web site for more info - http://www.national.com/quality/marking_conventions.html

Table 1. Pin Descriptions (LLP)

Pin #

Name

Description

1

Power supply voltage input to PFET and NFET switches for Buck 2

2

SW2

Buck 2 Switch Pin

3

PGND2

Buck 2 Power Ground

4

5

SGND

Signal GND

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3

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