ADR6

bit7

MSB

ADR5

bit6

ADR4

bit5

ADR3

I

2

C SLAVE address (chip address)

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

LSB

0

1

0

0

0

0

1

bit4

ack from slave

w ack

start

msb Chip Address lsb

msb Register Add lsb

msb

DATA

lsb

ack

ack stop

ack from slave

ack from slave

SCL

start

id = K¶

xx

w ack

addr = K¶00

DGGUHVV K¶00 data

ack

ack stop

SDA

rs

msb Chip Address lsb

r

ack

repeated start

data from slave

ack from master

r

id = K¶

xx

ack

rs

SCL

SDA

start

id = K¶

xx

w ack

addr = K¶02

DGGUHVV K¶02 data

ack

ack

stop

ack from slave

w ack

start

msb Chip Address lsb

msb Register Add lsb

msb

DATA

lsb

ack

ack

stop

ack from slave

ack from slave

LM3370

www.ti.com

SNVS406M – NOVEMBER 2005 – REVISED AUGUST 2011

I

W = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated startxx=36h

However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as

shown in the read cycle waveform.

I

DEVICE REGISTER INFORMATION

Table 3. Register Information

Register Name

Location

Type

Function

Control

00

R/W

Control signal for Buck 1 and

Buck 2

Buck 1

01

R/W

Output setting & Mode selection

for Buck 1

Buck 2

02

R/W

Output setting & Mode selection

for Buck 2 and POR disable

Copyright © 2005–2011, Texas Instruments Incorporated

Submit Documentation Feedback

17

Product Folder Links: LM3370