LM2647

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SNVS210E – MAY 2004 – REVISED JUNE 2005

Output 1V, 2A to Overload, VIN = 10V, L = 10µH, f = 300kHz, RLIM = 2k

Figure 14. Response to Severe Overload (Type B: current limit threshold first)

Application Information

CURRENT LIMIT RESISTOR

The timing scheme implemented in the LM2647 makes it possible for the IC to continue monitoring an

overcurrent condition and to respond appropriately every cycle. This is explained as follows.

Consider the LM2647 working under normal conditions, just before an overload occurs. After the end of a given

ON-pulse (say ‘ton1’), the LM2647 starts sampling the current in the low-side FET. This is the OFF-duration

called ‘toff1’ in this analysis. Therefore, if an overcurrent condition is detected during this OFF-duration ‘toff1’, the

controller will decide to omit the next ON-pulse (which would have occurred during the duration ‘ton2’). This is

done by setting an internal ‘overcurrent latch’ which will keep HDRV low. The LDRV will now not only stay high

during the present OFF-duration (‘toff1’) but during the duration of the next (omitted) ON-pulse (‘ton2’), and then

as expected also during the succeeding OFF-duration (‘toff2’). But the ‘overcurrent latch’ is reset at the very start

of the next OFF-duration ‘toff2’. Therefore if the overcurrent condition persists, it can be recognized during ‘toff2’

and a decision to skip the next ON-pulse (duration ‘ton3’) can be taken. Finally, several ON-pulses may get

skipped until the current in the lower FET falls below the current limit threshold.

Note that about 150ns after LDRV first goes high (start of low-side conduction), the current monitoring starts.

Therefore the peak current seen by the current limit detector is almost the same as the peak inductor current.

To set the value of the current limiting resistor (‘RLIM’, between ILIM pin and SW pin), the function of the ILIM

pin must be understood. Refer to Figure 15 to see how the voltage on the ILIM pin changes as current ramps up.

For this analysis note that the worst case has been taken here by using the minimum possible value of the

FET should be used. For example if the chosen low-side FET is the Si4420DY from Vishay, the typical Rds at

room temperature is 10m

Ω (but this is not the value to be used here). The MAX is the relevant number which is

13m

Ω. Now applying the thumbrule that at 100°C the Rds goes up typically 1.4 times (for 30V FETs), the Rds to

be used in the actual current limit calculation is 1.4*13m

Characteristics table) and Rds = 18.2m

Ω here will provide the lowest value of current limit (considering

tolerances and temperature for a chosen RLIM resistor). This current limit must obviously be higher than the

actual peak current in the converter under normal operation to ensure that full rated power can be delivered

under all conditions by the converter without ‘inadvertently’ hitting the worst case (lowest value) set current limit.

Copyright © 2004–2005, Texas Instruments Incorporated

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