Top View

Bottom View

A1

A3

Vin

EN

FB

SW

GND

Vin

EN

GND

SW

FB

C1

C3

B2

A3

A1

C3

C1

B2

LM3679

SNVS510A – SEPTEMBER 2007 – REVISED FEBRUARY 2008

www.ti.com

CONNECTION DIAGRAM AND PACKAGE MARK INFORMATION

Figure 3. 5 Bump Micro SMD and UR Package

Table 1. PIN DESCRIPTIONS

Pin #

Name

Description

A1

Power supply input. Connect to the input filter capacitor (Figure 1).

A3

GND

Ground pin.

C1

EN

Enable pin. The device is in shutdown mode when voltage to this pin is <0.4V and enabled

when >1.0V. Do not leave this pin floating.

C3

FB

Feedback analog input. Connect directly to the output filter capacitor ( FIGURE 1).

B2

SW

Switching node connection to the internal PFET switch and NFET synchronous rectifier.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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