6 GND

TOP VIEW

SW 2

EN 3

BOTTOM VIEW

VIN 1

5 SW

4 FB

6 GND

5 SW

4 FB

VIN 1

SW 2

EN 3

Top View

Bottom View

A1

A3

Vin

EN

FB

SW

GND

Vin

EN

GND

SW

FB

C1

C3

B2

A3

A1

C3

C1

B2

LM3677

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SNVS502E – MARCH 2007 – REVISED OCTOBER 2008

CONNECTION DIAGRAM AND PACKAGE MARK INFORMATION

Figure 4. 5-Bump micro SMD Package

NS Package Number TLA05FEA

Figure 5. 5 Bump Micro SMD Package

Figure 6. 6 Pin LLP Package

Pin #

Name

Description

A1

1

Power supply input. Connect to the input filter capacitor (Figure 1).

A3

6

GND

Ground pin.

C1

3

EN

Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4V and

enabled when > 1.0V. Do not leave this pin floating.

C3

4

FB

Feedback analog input. Connect directly to the output filter capacitor ( FIGURE 1).

B2

2, 5

SW

Switching node connection to the internal PFET switch and NFET synchronous

rectifier.

(1)

For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2007–2008, Texas Instruments Incorporated

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