TLC3574IPW datasheet(16/50 Pages) TI1

16 / 50 page

TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

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timing requirements over recommended operating free-air temperature range, AVDD = 5 V,

DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)

CSTART trigger

PARAMETERS

MIN

TYP

MAX

UNIT

td(12)

Delay time, delay from CSTART rising edge to EOC falling edge, at 10-pF

load

tw(4)

Pulse width of CSTART low, at 25-pF load (see Note 13)

t(sample_reg)+0.4

µs

td(13)

Delay time, delay from CSTART rising edge to CSTART falling edge, at 25-pF

load (see Note 13 and 14)

t(conv)+15

td(14)

Delay time, delay from CSTART rising edge to INT falling edge, at 10-pF

load (see Note 13 and 14)

t(conv)+15

t(conv)+21

td(15)

Delay time, delay from CSTART falling edge to INT rising edge, at 10-pF

load

NOTES: 13. The pulse width of the CSTART must be not less than the required sampling time.

The delay from CSTART rising edge to following CSTART falling edge must be not less than the required conversion time.

The delay from CSTART rising edge to the INT falling edge is equal to the conversion time.

14. The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling.

t(conv)

tw(4)

td(13)

td(12)

td(14)

td(15)

CSTART

EOC

INT

Figure 4. Critical Timing for Extended Sampling (CSTART Trigger)

TLC3574IPW Datasheet(PDF) 16 Page - Texas Instruments

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