WM1811A datasheet(140/328 Pages) WOLFSON

140 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

140

GENERAL PURPOSE INPUT/OUTPUT

The WM1811A provides a number of GPIO functions to enable interfacing and detection of external

hardware and to provide logic outputs to other devices. The input functions can be polled directly or

can be used to generate an Interrupt (IRQ) event. The GPIO and Interrupt circuits support the

following functions:



Alternate interface functions (AIF3)



Button detect (GPIO input)



Logic ‘1’ and logic ‘0’ output (GPIO output)



Interrupt (IRQ) status output



Over-Temperature detection



Microphone accessory status detection



Frequency Locked Loop (FLL) Lock status output



Sample Rate Conversion (SRC) Lock status output



Dynamic Range Control (DRC) Signal activity detection



Digital Core FIFO error status output



Clock output (SYSCLK divided by OPCLK_DIV)



Frequency Locked Loop (FLL) Clock output

GPIO CONTROL

For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO

pin (1, 8, 9, 10, 11). The pin direction, set by GPn_DIR, must be set according to function selected by

GPn_FN.

The digital audio interface AIF3 is supported using GPIO pins; the applicable pin functions are

selected by setting the corresponding GPn_FN register to 00h. The ADCLRCLK1 function for AIF1 is

supported on GPIO1. See Table 80 for the definition of which AIF function is available on each GPIO

pin.

See “Digital Audio Interface Control” for details of AIF2 and AIF3.

When a pin is configured as a GPIO input (GPn_DIR = 1), the logic level at the pin can be read from

the respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL bit.

A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled

on each pin by setting the respective GPn_DB bit.

When a pin is configured as a Logic Level output (GPn_DIR = 0, GPn_FN = 01h), its level can be set

to logic 0 or logic 1 using the GPn_LVL field.

When a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the

GPn_POL bit. When GPn_POL = 1, then the selected output function is inverted. In the case of Logic

Level output (GPn_FN = 01h), the external output will be the opposite logic level to GPn_LVL when

GPn_POL = 1.

A GPIO output can be either CMOS driven or Open Drain. This is selected on each pin using the

respective GPn_OP_CFG bit.

Internal pull-up and pull-down resistors may be enabled using the GPn_PU and GPn_PD fields; this

allows greater flexibility to interface with different signals from other devices.(Note that if GPn_PU and

GPn_PD are both set for any GPIO pin, then the pull-up and pull-down will be disabled.)

Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt

event. An interrupt event is triggered on the rising and falling edge of the GPIO input. The associated

interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See

“Interrupts” for more details of the Interrupt event handling.

WM1811A Datasheet(PDF) 140 Page - Wolfson Microelectronics plc

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