WM1811A datasheet(188/328 Pages) WOLFSON

188 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

188

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1568

(0620h)

Oversampling

ADC_OSR128

ADC / Digital Microphone Oversample

Rate Select

0 = Low Power

1 = High Performance

DAC_OSR128

DAC Oversample Rate Select

0 = Low Power

1 = High Performance

R1793

(0701h)

Pull Control

(MCLK2)

MCLK2_PU

MCLK2Pull-up enable

0 = Disabled

1 = Enabled

MCLK2_PD

MCLK2Pull-down enable

0 = Disabled

1 = Enabled

R1824

(0720h)

Pull Control

(1)

MCLK1_PU

MCLK1 Pull-up enable

0 = Disabled

1 = Enabled

MCLK1_PD

MCLK1 Pull-down enable

0 = Disabled

1 = Enabled

Table 112 System Clocking

BCLK AND LRCLK CONTROL

The digital audio interfaces (AIF1 and AIF2) use BCLK and LRCLK signals for synchronisation. In

master mode, these are output signals, generated by the WM1811A. In slave mode, these are input

signals to the WM1811A. It is also possible to support mixed master/slave operation.

The BCLK and LRCLK signals are controlled as illustrated in Figure 69. See the “Digital Audio

Interface Control” section for further details of the relevant control registers.

Figure 69 BCLK and LRCLK Control

WM1811A Datasheet(PDF) 188 Page - Wolfson Microelectronics plc

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