WM1811A datasheet(190/328 Pages) WOLFSON

190 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

190

Figure 71 FLL Configuration

The FLL is enabled using the FLLn_ENA register bit (where n = 1 for FLL1 and n = 2 for FLL2). Note

that the other FLL registers should be configured before enabling the FLL; the FLLn_ENA register bit

should be set as the final step of the FLLn enable sequence.

When changing FLL settings, it is recommended that the digital circuit be disabled via FLLn_ENA and

then re-enabled after the other register settings have been updated. When changing the input

reference frequency FREF, it is recommended that the FLL be reset by setting FLLn_ENA to 0.

The field FLLn_REFCLK_DIV provides the option to divide the input reference (MCLK, BCLK or

LRCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For

best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit -

should be selected.

The FLL output frequency is directly determined from FLLn_FRATIO, FLLn_OUTDIV and the real

number represented by N.K.

The integer value, N, is held in the FLLn_N register field. The fractional portion, K, is determined by

the ratio FLLn_THETA / FLLn_LAMBDA.

Note that the FLLn_EFS_ENA register bit must be enabled in fractional mode (ie. whenever

FLLn_THETA > 0).

The FLL output frequency is generated according to the following equation:

FOUT = (FVCO / FLLn_OUTDIV)

The FLLoperating frequency, FVCO is set according to the following equation:

FVCO = (FREF x N.K x FLLn_FRATIO)

FREF is the input frequency, as determined by FLLn_REFCLK_DIV.

FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.

Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed

across the full range of device operating conditions.

WM1811A Datasheet(PDF) 190 Page - Wolfson Microelectronics plc