WM1811A datasheet(193/328 Pages) WOLFSON

193 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

193

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R548 (0224h)

FLL1 Control (5)

FLL1_BYP

FLL1 Bypass Select

0 = Disabled

1 = Enabled

When FLL1_BYP is set, the FLL1

output is derived directly from

BCLK1. In this case, FLL1 can be

disabled.

4:3

FLL1_REFCLK_

DIV [1:0]

FLL1 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must

be divided down to <=13.5MHz.

For lower power operation, the

reference clock can be divided down

further if desired.

1:0

FLL1_REFCLK_

SRC [1:0]

FLL1 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK1

11 = BCLK1

R550 (0226h)

FLL1 EFS1

15:0

FLL1_LAMBDA

[15:0]

0000h

FLL Fractional multiply for FREF

This field sets the denominator

(dividing) part of the FLL1_THETA /

FLL1_LAMBDA ratio.

Coded as LSB = 1.

R551 (0227h)

FLL1 EFS2

2:1

Reserved - Do not change

FLL1_EFS_ENA

FLL Fractional Mode EFS enable

0 = Integer Mode

1 = Fractional Mode

This bit should be set to 1 when

FLL1_THETA > 0.

Table 115 FLL1 Register Map

WM1811A Datasheet(PDF) 193 Page - Wolfson Microelectronics plc

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