WM1811A datasheet(195/328 Pages) WOLFSON

195 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

195

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R582 (0246h)

FLL2 EFS1

15:0

FLL2_LAMBDA

[15:0]

0000h

FLL Fractional multiply for FREF

This field sets the denominator

(dividing) part of the FLL2_THETA /

FLL2_LAMBDA ratio.

Coded as LSB = 1.

R583 (0247h)

FLL2 EFS2

2:1

Reserved - Do not change

FLL2_EFS_ENA

FLL Fractional Mode EFS enable

0 = Integer Mode

1 = Fractional Mode

This bit should be set to 1 when

FLL2_THETA > 0.

Table 116 FLL2 Register Map

FREE-RUNNING FLL CLOCK

The FLL can generate a clock signal even when no external reference is available. However, it should

be noted that the accuracy of this clock is reduced, and a reference source should always be used

where possible. The free-running FLL modes are not sufficiently accurate for hi-fi ADC or DAC

operations, but are suitable for clocking most other functions, including the Charge Pump, DC Servo

and Class D loudspeaker driver. The free-running FLL operation is ideal for clocking the accessory

detection function during low-power standby operating conditions (see “External Accessory

Detection”).

If an accurate reference clock is initially available, then the FLL should be configured as described

above. The FLL will continue to generate a stable output clock after the reference input is stopped or

disconnected.

If no reference clock is available at the time of starting up the FLL, then an internal clock frequency of

approximately 12MHz can be generated by implementing the following sequence:



Enable the FLL Analogue Oscillator (FLLn_OSC_ENA = 1)



Set the FOUT clock divider to divide by 8 (FLLn_OUTDIV = 000111)



Configure the oscillator frequency by setting FLLn_FRC_NCO = 1 and

FLLn_FRC_NCO_VAL = 19h

Note that the free-running FLL mode is not suitable for hi-fi CODEC applications. In the absence of

any reference clock, the FLL output is subject to a very wide tolerance; see “Electrical Characteristics”

for details of the FLL accuracy.

Note that the free-running FLL clock is selected as SYSCLK using the registers noted inFigure 67.

The free-running FLL clock may be used to support analogue functions, for which the digital audio

interface is not used, and there is no applicable Sample Rate (fs). When SYSCLK is required for

circuits such the Class D, DC Servo or Charge Pump, then valid Sample Rate register settings are still

required, even though the digital audio interface is not active.

For correct functionality when SYSCLK_SRC = 0, valid settings are required for AIF1_SR and

AIF1CLK_RATE. In the case where SYSCLK_SRC = 1, then valid settings are required for AIF2_SR

and AIF2CLK_RATE.

The control registers applicable to FLL free-running modes are described in Table 117.

WM1811A Datasheet(PDF) 195 Page - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 195 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL