WM1811A datasheet(197/328 Pages) WOLFSON

197 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

197

EXAMPLE FLL CALCULATION

The following example illustrates how to derive the FLL1 registers to generate 12.288 MHz output

(FOUT) from a 12.000 MHz reference clock (FREF):



Set FLL1_REFCLK_DIV in order to generate FREF<=13.5MHz:

FLL1_REFCLK_DIV = 00 (divide by 1)



Set FLL1_OUTDIV for the required output frequency as shown in Table 113:-

FOUT = 12.288 MHz, therefore FLL1_OUTDIV = 7h (divide by 8)



Set FLL1_FRATIO for the given reference frequency as shown in Table 114:

FREF = 12MHz, therefore FLL1_FRATIO = 0h (divide by 1)



Calculate FVCO as given by FVCO = FOUT x FLL1_OUTDIV:-

FVCO = 12.288 x 8 = 98.304MHz



Calculate N.K as given by N.K = FVCO / (FLL1_FRATIO x FREF):

N.K = 98.304 / (1 x 12) = 8.192



Set FLL1_EFS_ENA according to whether N.K is an integer.

N.K has a fractional part, therefore FLL1_EFS_ENA = 1



Determine FLL1_N from the integer portion of N.K:-

FLL_N =8.



Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FRATIO x FREF, FVCO):

GCD(FLL)= GCD(1 x 12000000, 98304000) = 96000



Determine FLL1_THETA, as given by

FLL1_THETA = (FVCO - (FLL1_N x FLL1_FRATIO x FREF)) / GCD(FLL):

FLL1_THETA = (98304000 - (8 x 1 x 12000000)) / 96000

FLL1_THETA = 24 (0018h)



Determine FLL_LAMBDA, as given by

FLL1_LAMBDA = (FLL1_FRATIO x FREF) / GCD(FLL):

FLL1_LAMBDA = (1 x 12000000) / 96000

FLL1_LAMBDA = 125 (007Dh)

WM1811A Datasheet(PDF) 197 Page - Wolfson Microelectronics plc