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WM1811A Datasheet(PDF) 196 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 196 Page - Wolfson Microelectronics plc |
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196 / 328 page  WM1811A Production Data w PD, November 2013, Rev 4.1 196 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R544 (0220h) FLL1 Control (1) 1 FLL1_OSC_ENA 0 FLL1Oscillator enable 0 = Disabled 1 = Enabled (Note that this field is required for free-running FLL1 modes only) R548 (0224h) FLL1 Control (5) 12:7 FLL1_FRC_NCO _VAL [5:0] 19h FLL1 Forced oscillator value Valid range is 000000 to 111111 0x19h (011001) = 12MHz approx (Note that this field is required for free-running FLL modes only) 6 FLL1_FRC_NCO 0 FLL1Forced control select 0 = Normal 1 = FLL1 oscillator controlled by FLL1_FRC_NCO_VAL (Note that this field is required for free-running FLL modes only) R576 (0240h) FLL2 Control (1) 1 FLL2_OSC_ENA 0 FLL2 Oscillator enable 0 = Disabled 1 = Enabled (Note that this field is required for free-running FLL2 modes only) R580 (0244h) FLL2 Control (5) 12:7 FLL2_FRC_NCO _VAL [5:0] 19h FLL2 Forced oscillator value Valid range is 000000 to 111111 0x19h (011001) = 12MHz approx (Note that this field is required for free-running FLL modes only) 6 FLL2_FRC_NCO 0 FLL2 Forced control select 0 = Normal 1 = FLL2 oscillator controlled by FLL2_FRC_NCO_VAL (Note that this field is required for free-running FLL modes only) Table 117 FLL Free-Running Mode GPIO OUTPUTS FROM FLL For each FLL, the WM1811A has an internal signal which indicates whether the FLL Lock has been achieved. The FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see “Interrupts”. The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See “General Purpose Input/Output” for details of how to configure a GPIO pin to output the FLL Lock signal. The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the FLL Clock may be output even if the FLL is not selected as the WM1811A SYSCLK source. The FLL clocking configuration is illustrated in Figure 70. See “General Purpose Input/Output” for details of how to configure a GPIO pin to output the FLL Clock. |
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