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WM1811A Datasheet(PDF) 198 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 198 Page - Wolfson Microelectronics plc |
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198 / 328 page ![]() WM1811A Production Data w PD, November 2013, Rev 4.1 198 EXAMPLE FLL SETTINGS Table 118 provides example FLL settings for generating common SYSCLK frequencies from a variety of low and high frequency reference inputs. FSOURCE FOUT(MHz) FREF Divider N.K FRATIO FVCO (MHz) OUTDIV FLLn_N FLLn_ EFS_EN A FLLn_ THETA FLLn_ LAMBDA 32.000kHz 12.288 1 192 16 98.304 8 0C0h 0 32.000kHz 11.2896 1 176.4 16 90.3168 8 0B0h 1 0002h 0005h 32.768kHz 12.288 1 187.5 16 98.304 8 0BBh 1 0001h 0002h 32.768kHz 11.2896 1 172.2656 16 90.3168 8 0ACh 1 0011h 0040h 44.1 kHz 11.2896 1 128 16 90.3168 8 080h 0 48 kHz 12.288 1 128 16 98.304 8 080h 0 128 kHz 2.048 1 96 8 98.304 48 060h 0 128 kHz 12.288 1 96 8 98.304 8 060h 0 512 kHz 2.048 1 96 2 98.304 48 060h 0 512 kHz 12.288 1 96 2 98.304 8 060h 0 1.4112 MHz 11.2896 1 64 1 90.3168 8 040h 0 2.8224 MHz 11.2896 1 32 1 90.3168 8 020h 0 1.536 MHz 12.288 1 64 1 98.304 8 040h 0 3.072 MHz 12.288 1 32 1 98.304 8 020h 0 11.2896 12.288 1 8.7075 1 98.304 8 008h 1 0068h 0093h 12.000MHz 12.288 1 8.192 1 98.304 8 008h 1 0018h 007Dh 12.000MHz 11.2896 1 7.5264 1 90.3168 8 007h 1 0149h 0271h 12.288MHz 12.288 1 8 1 98.304 8 008h 0 12.288MHz 11.2896 1 7.35 1 90.3168 8 007h 1 0007h 0014h 13.000MHz 12.288 1 7.5618 1 98.304 8 007h 1 0391h 0659h 13.000MHz 11.2896 1 6.9474 1 90.3168 8 006h 1 1E12h 1FBDh 19.200MHz 12.288 2 10.24 1 98.304 8 00Ah 1 0006h 0019h 19.200MHz 11.2896 2 9.408 1 90.3168 8 009h 1 0033h 007Dh 24 MHz 12.288 2 8.192 1 98.304 8 008h 1 0018h 007Dh 24 MHz 11.2896 2 7.5264 1 90.3168 8 007h 1 0149h 0271h 26 MHz 12.288 2 7.5618 1 98.304 8 007h 1 0391h 0659h 26 MHz 11.2896 2 6.9474 1 90.3168 8 006h 1 1E12h 1FBDh 27 MHz 12.288 2 7.2818 1 98.304 8 007h 1 013Dh 0465h 27 MHz 11.2896 2 6.6901 1 90.3168 8 006h 1 050Eh 0753h FOUT = (FSOURCE / FREF Divider) * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above. See Table 115 and Table 116 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 118 Example FLL Settings |
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