WM1811A datasheet(200/328 Pages) WOLFSON

200 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

200

SAMPLE RATE CONVERTER RESTRICTIONS

The following restrictions apply to the configuration of the WM1811A Sample Rate Converters.

No SRC capability when using 88.2kHz or 96kHz AIF input (DAC playback). If either interface is

configured for 88.2kHz or 96kHz sample rate, then the digital mixing core must also be configured for

this sample rate. Sample Rate Conversion cannot be supported in this mode, therefore AIF output is

not supported at any sample rate under these conditions.

Restricted Sample Rate options when AIF1 and AIF2 are not synchronised. When a different

clock source is used for AIF1CLK and AIF2CLK, then the AIF to which the SYSCLK is synchronised

cannot be mixed sample rates.



If AIF1CLK_SRC ≠ AIF2CLK_SRC



And SYSCLK_SRC =0



Then AIF1DAC_DIV and AIF1ADC_DIV must be set to 000

SAMPLE RATE CONVERTER CONFIGURATION ERROR INDICATION

The WM1811A verifies the register settings relating to Clocking, Sample Rates and Sample Rate

Conversion. If an invalid configuration is attempted, then the SR_ERROR register will indicate the

error by showing a non-zero value. This read-only field may be checked to confirm that the WM1811A

can support the selected Clocking and Sample Rate settings.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R530 (0212h)

Rate Status

3:0

SR_ERROR

[3:0]

0000

Sample Rate Configuration status

Indicates an error with the register settings

related to sample rate configuration

0000 = No errors

0001 = Invalid sample rate

0010 = Invalid AIF divide

0011 = ADC and DAC divides both set in an

interface

0100 = Invalid combination of AIF divides

and sample-rate

0101 = Invalid set of enables for 96kHz

mode

0110 = Invalid SYSCLK rate (derived from

AIF1CLK_RATE or AIF2CLK_RATE)

0111 = Mixed ADC and DAC rates in

SYSCLK AIF when AIFs are asynchronous

1000 = Invalid combination of sample rates

when both AIFs are from the same clock

source

1001 = Invalid combination of mixed

ADC/DAC AIFs when both from the same

clock source

Table 119 Sample Rate Converter Configuration Status

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