WM1811A datasheet(254/328 Pages) WOLFSON

254 / 328 page

WM1811A

Production Data

PD, November 2013, Rev 4.1

254

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

HPOUT1R_DLY

Enables HPOUT1R intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should be set to 1 after the output signal path

has been configured, and before DC offset cancellation is scheduled. This bit

should be set with at least 20us delay after HPOUT1R_ENA.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R197 (C5h)

Class D Test

(5)

SPKOUT_CLK_S

Selects the source for the CLASSD speaker clock

0: selects undithered clock

1: selects dithered clock

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R208 (D0h)

Mic Detect 1

15:12

MICD_BIAS_STA

RTTIME [3:0]

0111

Mic Detect Bias Startup Delay

(If MICBIAS2 is not enabled already, this field selects the delay time allowed

for MICBIAS2 to startup prior to performing the MICDET function.)

0000 = 0ms (continuous)

0001 = 0.25ms

0010 = 0.5ms

0011 = 1ms

0100 = 2ms

0101 = 4ms

0110 = 8ms

0111 = 16ms

1000 = 32ms

1001 = 64ms

1010 = 128ms

1011 = 256ms

1100 to 1111 = 512ms

11:8

MICD_RATE [3:0]

0110

Mic Detect Rate

(Selects the delay between successive Mic Detect measurements.)

0000 = 0ms (continuous)

0001 = 0.25ms

0010 = 0.5ms

0011 = 1ms

0100 = 2ms

0101 = 4ms

0110 = 8ms

0111 = 16ms

1000 = 32ms

1001 = 64ms

1010 = 128ms

1011 = 256ms

1100 to 1111 = 512ms

MICD_DBTIME

Mic Detect De-bounce

0 = 2 measurements

1 = 4 measurements

WM1811A Datasheet(PDF) 254 Page - Wolfson Microelectronics plc

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