WM1811A datasheet(257/328 Pages) WOLFSON

257 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

257

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

AIF1ADC_DIV

[2:0]

000

Selects the AIF1 output path sample rate relative to the AIF1 input path

sample rate.

This field should only be changed from default in modes where the AIF1

output path sample rate is slower than the AIF1 input path sample rate.

000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R516 (0204h)

AIF2

Clocking (1)

4:3

AIF2CLK_SRC

[1:0]

AIF2CLK Source Select

00 = MCLK1

01 = MCLK2

10 = FLL1

11 = FLL2

AIF2CLK_INV

AIF2CLK Invert

0 = AIF2CLK not inverted

1 = AIF2CLK inverted

AIF2CLK_DIV

AIF2CLK Divider

0 = AIF2CLK

1 = AIF2CLK / 2

AIF2CLK_ENA

AIF2CLK Enable

0 = Disabled

1 = Enabled

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R520 (0208h)

Clocking (1)

TOCLK_ENA

Slow Clock (TOCLK) Enable

0 = Disabled

1 = Enabled

This clock is required for zero-cross timeout.

AIF1DSPCLK_EN

AIF1 Processing Clock Enable

0 = Disabled

1 = Enabled

AIF2DSPCLK_EN

AIF2 Processing Clock Enable

0 = Disabled

1 = Enabled

SYSDSPCLK_EN

Digital Mixing Processor Clock Enable

0 = Disabled

1 = Enabled

SYSCLK_SRC

SYSCLK Source Select

0 = AIF1CLK

1 = AIF2CLK

WM1811A Datasheet(PDF) 257 Page - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 257 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL