WM1811A datasheet(261/328 Pages) WOLFSON

261 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

261

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R546 (0222h)

FLL1 Control

(3)

15:0

FLL1_THETA

[15:0]

0000_0000_00

00_0000

FLL Fractional multiply for FREF

This field sets the numerator (multiply) part of the FLL1_THETA /

FLL1_LAMBDA ratio.

Coded as LSB = 1.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R547 (0223h)

FLL1 Control

(4)

14:5

FLL1_N [9:0]

00_0000_0000 FLL Integer multiply for FREF

(LSB = 1)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R548 (0224h)

FLL1 Control

(5)

FLL1_BYP

FLL1 Bypass Select

0 = Disabled

1 = Enabled

When FLL1_BYP is set, the FLL1 output is derived directly from BCLK1. In

this case, FLL1 can be disabled.

12:7

FLL1_FRC_NCO

_VAL [5:0]

01_1001

FLL1 Forced oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for free-running FLL modes only)

FLL1_FRC_NCO

FLL1 Forced control select

0 = Normal

1 = FLL1 oscillator controlled by FLL1_FRC_NCO_VAL

(Note that this field is required for free-running FLL modes only)

4:3

FLL1_REFCLK_D

IV [1:0]

FLL1 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down to <=13.5MHz.

For lower power operation, the reference clock can be divided down further if

desired.

1:0

FLL1_REFCLK_S

RC [1:0]

FLL1 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK1

11 = BCLK1

WM1811A Datasheet(PDF) 261 Page - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 261 Page - Wolfson Microelectronics plc

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