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WM1811A Datasheet(PDF) 264 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 264 Page - Wolfson Microelectronics plc |
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264 / 328 page ![]() WM1811A Production Data w PD, November 2013, Rev 4.1 264 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R582 (0246h) FLL2 EFS 1 15:0 FLL2_LAMBDA [15:0] 0000_0000_00 00_0000 FLL Fractional multiply for FREF This field sets the denominator (dividing) part of the FLL2_THETA / FLL2_LAMBDA ratio. Coded as LSB = 1. Register 0246h FLL2 EFS 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R583 (0247h) FLL2 EFS 2 2 Reserved 1 Reserved - do not change 1 Reserved 1 Reserved - do not change 0 FLL2_EFS_ENA 0 FLL Fractional Mode EFS enable 0 = Integer Mode 1 = Fractional Mode This bit should be set to 1 when FLL2_THETA > 0. Register 0247h FLL2 EFS 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R768 (0300h) AIF1 Control (1) 15 AIF1ADCL_SRC 0 AIF1 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 14 AIF1ADCR_SRC 1 AIF1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 13 AIF1ADC_TDM 0 AIF1 transmit (ADC) TDM Enable 0 = Normal ADCDAT1 operation 1 = TDM enabled on ADCDAT1 12 AIF1ADC_TDM_ CHAN 0 AIF1 transmit (ADC) TDM Slot Select 0 = Slot 0 1 = Slot 1 8 AIF1_BCLK_INV 0 BCLK1 Invert 0 = BCLK1 not inverted 1 = BCLK1 inverted Note that AIF1_BCLK_INV selects the BCLK1 polarity in Master mode and in Slave mode. 6:5 AIF1_WL [1:0] 10 AIF1 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - 8-bit modes can be selected using the “Companding” control bits. 4:3 AIF1_FMT [1:0] 10 AIF1 Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode Register 0300h AIF1 Control (1) |
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