Electronic Components Datasheet Search
  English  ▼

X  

WM1811A Datasheet(PDF) 264 Page - Wolfson Microelectronics plc

Part # WM1811A
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 264 Page - Wolfson Microelectronics plc

Back Button WM1811A Datasheet HTML 260Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 261Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 262Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 263Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 264Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 265Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 266Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 267Page - Wolfson Microelectronics plc WM1811A Datasheet HTML 268Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 264 / 328 page
background image
WM1811A
Production Data
w
PD, November 2013, Rev 4.1
264
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R582 (0246h)
FLL2 EFS 1
15:0
FLL2_LAMBDA
[15:0]
0000_0000_00
00_0000
FLL Fractional multiply for FREF
This field sets the denominator (dividing) part of the FLL2_THETA /
FLL2_LAMBDA ratio.
Coded as LSB = 1.
Register 0246h FLL2 EFS 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R583 (0247h)
FLL2 EFS 2
2
Reserved
1
Reserved - do not change
1
Reserved
1
Reserved - do not change
0
FLL2_EFS_ENA
0
FLL Fractional Mode EFS enable
0 = Integer Mode
1 = Fractional Mode
This bit should be set to 1 when FLL2_THETA > 0.
Register 0247h FLL2 EFS 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R768 (0300h)
AIF1 Control
(1)
15
AIF1ADCL_SRC
0
AIF1 Left Digital Audio interface source
0 = Left ADC data is output on left channel
1 = Right ADC data is output on left channel
14
AIF1ADCR_SRC
1
AIF1 Right Digital Audio interface source
0 = Left ADC data is output on right channel
1 = Right ADC data is output on right channel
13
AIF1ADC_TDM
0
AIF1 transmit (ADC) TDM Enable
0 = Normal ADCDAT1 operation
1 = TDM enabled on ADCDAT1
12
AIF1ADC_TDM_
CHAN
0
AIF1 transmit (ADC) TDM Slot Select
0 = Slot 0
1 = Slot 1
8
AIF1_BCLK_INV
0
BCLK1 Invert
0 = BCLK1 not inverted
1 = BCLK1 inverted
Note that AIF1_BCLK_INV selects the BCLK1 polarity in Master mode and in
Slave mode.
6:5
AIF1_WL [1:0]
10
AIF1 Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Note - 8-bit modes can be selected using the “Companding” control bits.
4:3
AIF1_FMT [1:0]
10
AIF1 Digital Audio Interface Format
00 = Right justified
01 = Left justified
10 = I2S Format
11 = DSP Mode
Register 0300h AIF1 Control (1)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com