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WM1811A Datasheet(PDF) 262 Page - Wolfson Microelectronics plc

Part # WM1811A
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 262 Page - Wolfson Microelectronics plc

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WM1811A
Production Data
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PD, November 2013, Rev 4.1
262
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R550 (0226h)
FLL1 EFS 1
15:0
FLL1_LAMBDA
[15:0]
0000_0000_00
00_0000
FLL Fractional multiply for FREF
This field sets the denominator (dividing) part of the FLL1_THETA /
FLL1_LAMBDA ratio.
Coded as LSB = 1.
Register 0226h FLL1 EFS 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R551 (0227h)
FLL1 EFS 2
2
Reserved
1
Reserved - do not change
1
Reserved
1
Reserved - do not change
0
FLL1_EFS_ENA
0
FLL Fractional Mode EFS enable
0 = Integer Mode
1 = Fractional Mode
This bit should be set to 1 when FLL1_THETA > 0.
Register 0227h FLL1 EFS 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R576 (0240h)
FLL2Control
(1)
1
FLL2_OSC_ENA
0
FLL2 Oscillator enable
0 = Disabled
1 = Enabled
(Note that this field is required for free-running FLL2 modes only)
0
FLL2_ENA
0
FLL2 Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the FLL2 enable sequence, ie. after the
other FLL registers have been configured.
Register 0240h FLL2Control (1)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R577 (0241h)
FLL2Control
(2)
13:8
FLL2_OUTDIV
[5:0]
00_0000
FLL2 FOUT clock divider
000000 = Reserved
000001 = Reserved
000010 = Reserved
000011 = 4
000100 = 5
000101 = 6
…
111110 = 63
111111 = 64
(FOUT = FVCO / FLL2_OUTDIV)
2:0
FLL2_FRATIO
[2:0]
000
FLL2 FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
Register 0241h FLL2Control (2)



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