WM1811A datasheet(263/328 Pages) WOLFSON

263 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

263

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R578 (0242h)

FLL2Control

(3)

15:0

FLL2_THETA

[15:0]

0000_0000_00

00_0000

FLL Fractional multiply for FREF

This field sets the numerator (multiply) part of the FLL2_THETA /

FLL2_LAMBDA ratio.

Coded as LSB = 1.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R579 (0243h)

FLL2 Control

(4)

14:5

FLL2_N [9:0]

00_0000_0000 FLL Integer multiply for FREF

(LSB = 1)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R580 (0244h)

FLL2Control

(5)

FLL2_BYP

FLL2 Bypass Select

0 = Disabled

1 = Enabled

When FLL2_BYP is set, the FLL2 output is derived directly from BCLK2. In

this case, FLL2 can be disabled.

12:7

FLL2_FRC_NCO

_VAL [5:0]

01_1001

FLL2 Forced oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for free-running FLL modes only)

FLL2_FRC_NCO

FLL2 Forced control select

0 = Normal

1 = FLL2 oscillator controlled by FLL2_FRC_NCO_VAL

(Note that this field is required for free-running FLL modes only)

4:3

FLL2_REFCLK_D

IV [1:0]

FLL2 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down to <=13.5MHz.

For lower power operation, the reference clock can be divided down further if

desired.

1:0

FLL2_REFCLK_S

RC [1:0]

FLL2 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK2

11 = BCLK2

WM1811A Datasheet(PDF) 263 Page - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 263 Page - Wolfson Microelectronics plc

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