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GMS36 Datasheet(PDF) 43 Page - Hynix Semiconductor |
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GMS36 Datasheet(HTML) 43 Page - Hynix Semiconductor |
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43 / 109 page  4-10 Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of f OSC/6 cycle comes in the first step of WDT after WDT reset. If this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. The overflow time is 6 Ø2 13/f OSC (108.026ms at fOSC=455KHz.) 8 Ø6Ø213/f OSC (108.026ms at fOSC = 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR), Power-on reset pulse or Low VDD detection pulse. * It is constantly reset in STOP mode. When STOP is released, counting is restarted. f OSC/6 or fOSC/48 CPU reset Reset by instruction Power-On Reset Low VDD Detection Binary counter(14 steps) RESET (edge-trigger) Fig. 4-7 Block Diagram of Watch-dog Timer Chapter 4. FUNCTIONAL DESCRIPTION |
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