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GMS87C2020 Datasheet(PDF) 35 Page - Hynix Semiconductor |
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GMS87C2020 Datasheet(HTML) 35 Page - Hynix Semiconductor |
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35 / 92 page  Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 35 11.4 Data Memory (GMS81C2120) Figure 11-8 shows the internal Data Memory space avail- able. Data Memory is divided into two groups, a user RAM(including Stack) and control registers. Figure 11-8 Data Memory Map User Memory The GMS81C2120 has 448 × 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral in- terface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit ma- nipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio ÷16 Note: Several names are given at same address. Refer to USER MEMORY CONTROL REGISTERS 0000H 00BFH 00C0H 00FFH PAGE0 USER MEMORY 0100H 01FFH ( including STACK ) PAGE1 Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H 0C4H 0C5H 0C6H 0C7H 0CAH 0CBH 0CCH 0CDH R0 R0IO R2 R2IO R3 R3IO R5 R5IO R6 R6IO R/W W R/W W R/W W R/W W R/W W Undefined 0000_0000 Undefined 0000_0000 Undefined ---0_0000 Undefined 0000_0--- Undefined 0000_0000 byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte 0D0H 0D1H 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM1HR BUR R/W R W R R/W W W R R R/W W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH 0EFH SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0001 Undefined 0000_---- 0000_---- 0000_---- 0000_---- ----_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0F4H 0F6H 0F7H 0F9H 0FAH 0FBH R0FUNC R5FUNC R6FUNC R5NODR SCMR RA W W W W R/W R ----_0000 0000_0--- 0000_0000 0000_0--- ---0_0000 Undefined byte byte byte byte byte - Table 11-4 Control Registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. |
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