GMS87C2020 datasheet(53/92 Pages) HYNIX

53 / 92 page

Hyundai Micro Electronics

GMS81C2020/GMS81C2120

Nov. 1999 Ver 0.0

preliminary

These timers have each 8-bit count register and data regis-

ter. The count register is increased by every internal or ex-

ternal clock input. The internal clock has a prescaler divide

ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con-

trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and

1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-

ister TM1). In the Timer 0, timer register T0 increases

from 00H until it matches TDR0 and then reset to 00H. The

match output of Timer 0 generates Timer 0 interrupt

(latched in T0IF bit). As TDRx and Tx register are in same

address, when reading it as a Tx, written to TDRx.

In counter function, the counter is increased every 0-to-

1(1-to-0) (rising & falling edge) transition of EC0 pin. In

order to use counter function, the bit EC0 of the R0 Func-

tion Selection Register

(R0FUNC.2) is set to "1". The Timer

0 can be used as a counter by pin EC0 input, but Timer 1

can not.

Figure 15-3 Counting Example of Timer Data Registers

Figure 15-4 Timer Count Operation

Timer 1 (T1IF)

Interrupt

TDR1

TIME

Occur interrupt

Interrupt period

n-1

PCP

= PCP x (n+1)

Timer 1 (T1IF)

Interrupt

TDR1

TIME

Occur interrupt

stop

clear & start

disable

enable

Start & Stop

T1ST

T1CN

Control count

T1ST = 0

T1ST = 1

T1CN = 0

T1CN = 1

GMS87C2020 Datasheet(PDF) 53 Page - Hynix Semiconductor

GMS87C2020 Datasheet(HTML) 53 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL