SSM2160/SSM2161

REV. A

–5–

Figure 4. Timing Diagrams

NOTES

1. An idle HI (CLK-H) or idle LO (CLK-LO) clock may be used. Data is latched

on the negative edge.

2. For SPI or microwire three-wire bus operation, tie LD to WRITE and use

WRITE

pulse to drive both pins. (This generates an automatic internal LD

signal.)

transition to the idle state.

4. The first data byte selects an address (MSB HI), and subsequent MSB LO states

set gain levels. Refer to the Address/Data Decoding Truth Table.

5. Data must be sent MSB first.

6. The SSM2160/SSM2161 will power up with all channel outputs muted, thus

preventing "start-up blasting." To insure a smooth start-up, data should be sent

to first initialize the Master DAC, then to set the individual channel DAC levels.

Table I. Timing Description

Timing

Typical

Symbol

Description

Time (ns)

Input Clock Pulse Width

TBD

Data Setup Time

TBD

Data Hold Time

TBD

Negative CLK-LO Edge to End of Write

TBD

End of Load Pulse to Next Write

TBD

Start of Write to Data

TBD

End of Write to Start of Load

TBD

Load Pulse Width

TBD

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

1

1

1

1

CLK

DATA

WRITE

LD

0

0

1

1

0

1

1

0

CLK

DATA

WRITE

LD

OBSOLETE