D844 datasheet(15/20 Pages) AD

15 / 20 page

AD844

Rev. F | Page 15 of 20

USING THE AD844

BOARD LAYOUT

As with all high frequency circuits considerable care must be

used in the layout of the components surrounding the AD844.

A ground plane, to which the power supply decoupling capaci-

tors are connected by the shortest possible leads, is essential to

achieving clean pulse response. Even a continuous ground plane

exhibits finite voltage drops between points on the plane, and

this must be kept in mind when selecting the grounding points.

In general, decoupling capacitors should be taken to a point

close to the load (or output connector) because the load

currents flow in these capacitors at high frequencies. The +IN

and −IN circuits (for example, a termination resistor and Pin 3)

must be taken to a common point on the ground plane close to

the amplifier package.

Use low impedance 0.22 μF capacitors (AVX SR305C224KAA

or equivalent) wherever ac coupling is required. Include either

ferrite beads and/or a small series resistance (approximately

4.7 Ω) in each supply line.

INPUT IMPEDANCE

At low frequencies, negative feedback keeps the resistance at the

inverting input close to zero. As the frequency increases, the

impedance looking into this input increases from near zero to

the open-loop input resistance, due to bandwidth limitations,

making the input seem inductive. If it is desired to keep the

input impedance flatter, a series RC network can be inserted

across the input. The resistor is chosen so that the parallel sum

of it and R2 equals the desired termination resistance. The capacit-

ance is set so that the pole determined by this RC network is

about half the bandwidth of the op amp. This network is not

important if the input resistor is much larger than the termination

used, or if frequencies are relatively low. In some cases, the

small peaking that occurs without the network can be of use in

extending the −3 dB bandwidth.

DRIVING LARGE CAPACITIVE LOADS

Capacitive drive capability is 100 pF without an external net-

work. With the addition of the network shown in Figure 34,

the capacitive drive can be extended to over 10,000 pF, limited

by internal power dissipation. With capacitive loads, the output

speed becomes a function of the overdriven output current limit.

Because this is roughly ±100 mA, under these conditions, the

maximum slew rate into a 1000 pF load is ±100 V/μs. Figure 35

shows the transient response of an inverting amplifier (R1 =

R2 = 1 kΩ) using the feedforward network shown in Figure 34,

driving a load of 1000 pF.

AD844

VOUT

750Ω

22pF

Figure 34. Feedforward Network for Large Capacitive Loads

500ns

100

Figure 35. Driving 1000 pF CL with Feedforward Network of Figure 34

SETTLING TIME

Settling time is measured with the circuit of Figure 36. This

circuit employs a false summing node, clamped by the two

Schottky diodes, to create the error signal and limit the input

signal to the oscilloscope. For measuring settling time, the ratio

of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ, and

RL = 500 Ω. For the gain of −10, R5 = 50 Ω, R6 = 500 Ω, and RL

was not used because the summing network loads the output

with approximately 275 Ω. Using this network in a unity-gain

configuration, settling time is 100 ns to 0.1% for a –5 V to +5 V

step with CL = 10 pF.

VIN

VOUT

TO SCOPE

(TEK 7A11 FET PROBE)

NOTES

1. D1, D2 IN6263 OR EQUIVALENT SCHOTTKY DIODE.

AD844

Figure 36. Settling Time Test Fixture

D844 Datasheet(PDF) 15 Page - Analog Devices

D844 Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL