D844 datasheet(16/20 Pages) AD

16 / 20 page

AD844

Rev. F | Page 16 of 20

DC ERROR CALCULATION

Figure 37 shows a model of the dc error and noise sources for

the AD844. The inverting input bias current, IBN, flows in the

feedback resistor. IBP, the noninverting input bias current, flows

in the resistance at Pin 3 (RP), and the resulting voltage (plus

any offset voltage) appears at the inverting input. The total

error, VO, at the output is:

()

⎟

⎠

⎞

⎜

⎝

⎛ +

Because IBN and IBP are unrelated both in sign and magnitude,

inserting a resistor in series with the noninverting input does

not necessarily reduce dc error and may actually increase it.

INN

INP

IBP

IBN

VOS

AD844

RIN

Figure 37. Offset Voltage and Noise Model for the AD844

NOISE

Noise sources can be modeled in a manner similar to the dc bias

currents, but the noise sources are INN, INP, VN, and the amplifier

induced noise at the output, VON, is:

()

()2

⎟

⎠

⎞

⎜

⎝

⎛ +

Overall noise can be reduced by keeping all resistor values to a

minimum. With typical numbers, R1 = R2 = 1 kΩ, RP = 0 Ω,

VN = 2 nV/√Hz, INP = 10 pA/√Hz, INN = 12 pA/√Hz, and VON

calculates to 12 nV/√Hz. The current noise is dominant in this

case, because it is in most low gain applications.

VIDEO CABLE DRIVER USING ±5 V SUPPLIES

The AD844 can be used to drive low impedance cables. Using

±5 V supplies, a 100 Ω load can be driven to ±2.5 V with low

distortion. Figure 38 shows an illustrative application that

provides a noninverting gain of +2, allowing the cable to be

reverse-terminated while delivering an overall gain of +1 to the

load. The −3 dB bandwidth of this circuit is typically 30 MHz.

Figure 39 shows a differential gain and phase test setup. In video

applications, differential-phase and differential-gain characteris-

tics are often important. Figure 40 shows the variation in phase as

the load voltage varies. Figure 41 shows the gain variation.

VIN

50Ω

300Ω

+5V

–5V

2.2µF

ZO = 50Ω

VOUT

Figure 38. The AD844 as a Cable Driver

HP8753A

NETWORK

ANALYZER

HP11850C

SPLITTER

CIRCUIT

UNDER

TEST

HP3314A

STAIRCASE

GENERATOR

VOUT

VIN

OUT

RF OUT

RF IN

EXT

TRIG

SYNC OUT

50Ω

(TERMINATOR)

OUT

470Ω

Figure 39. Differential Gain/Phase Test Setup

VOUT (IRE)

0.3

0.2

–0.3

0.1

–0.1

–0.2

IRE = 7.14mV

Figure 40. Differential Phase for the Circuit of Figure 38

VOUT (IRE)

0.06

0.04

–0.06

018

0.02

–0.02

–0.04

IRE = 7.14mV

Figure 41. Differential Gain for the Circuit of Figure 38

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