IMP8

©

1999 IMP, Inc.

408-432-9100/www.impweb.com

5

Detailed Description

Reset Timing and Manual Reset (MR)

The reset signal is asserted–LOW for the IMP811 and HIGH for

has risen above the threshold.

A logic low on MR asserts RESET LOW on the IMP811 and HIGH

on the IMP812. MR is internally pulled high through a 20k

Ω

resistor and can be driven by TTL/CMOS gates or with open

collector/drain outputs. MR can be left open if not used.

MR may be connected to a normally-open switch connected to

ground without an external debounce circuit.

For added noise rejection, a 0.1µF capacitor from MR to Ground

can be added.

Figure 1. Reset Timing and Manual Reset (MR)

5V

0V

5V

0V

MR

140ms

minimum

Active Reset

Timeout Period

Active Reset

Timeout Period

5V

0V

RESET

5V

0V

RESET

IMP811

IMP812

811/12_03.eps