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80960CF-33 Datasheet(PDF) 45 Page - Intel Corporation |
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80960CF-33 Datasheet(HTML) 45 Page - Intel Corporation |
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45 / 77 page ![]() PRELIMINARY 39 A 80960CF-40, -33, -25, -16 Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform Figure 13. Hold Acknowledge Timings PCLK2:1 1.5 V 1.5 V 1.5 V Valid TIS TIH NMI, XINT7:0 Min Min F_CX013A 1.5 V 1.5 V PCLK2:1 1.5 V 1.5 V 1.5 V Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA Min Max Min Max Valid 1.5 V Valid TOF TOV HOLD TIS TIH 1.5 V 1.5 V TIH TIS HOLDA TOV Min Min Min Min Max Min Max Min F_CX014A 1.5 V 1.5 V 1.5 V NOTES: 1. TOV TOH - OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay (TOV); minimum output delay is referred to as Output Hold (TOH). 2. TOF - OUTPUT FLOAT DELAY - Output float condition occurs when the maximum output current becomes less that ILO in magnitude. 3. TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 1.5 V TOV |
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