80960CF-33 datasheet(48/77 Pages) INTEL

48 / 77 page

PRELIMINARY

80960CF-40, -33, -25, -16

Figure 18. ICC vs. Frequency and Temperature—80960CF-33, -25, -16

Figure 19. ICC vs. Frequency and Temperature—80960CF-40

900

TC = 100° C

TC = 0° C

fPCLK (MHz)

ICC - ICC under test conditions

F_CX020A

1100

fPCLK (MHz)

ICC - ICC under test conditions

F_CX020A

TC = 85° C

5.0

RESET, BACKOFF AND HOLD

ACKNOWLEDGE

Table 19 lists the condition of each processor output

pin while RESET is asserted (low). Table 20 lists the

condition of each processor output pin while HOLDA

is asserted (high).

In Table 20, with regard to bus output pin state only,

the Hold Acknowledge state takes precedence over

the reset state. Although asserting the RESET pin

internally resets the processor, the processor’s bus

output pins do not enter the reset state if Hold

Acknowledge has been granted to a previous HOLD

request

(HOLDA

active).

Furthermore,

the

processor grants new HOLD requests and enters the

Hold Acknowledge state even while in reset.

For example, if HOLD is asserted while HOLDA is

inactive and the processor is in the reset state, the

processor’s bus pins enter the Hold Acknowledge

state and HOLDA is granted. The processor is not

able to perform memory accesses until the HOLD

request is removed, even if the RESET pin is brought

high. This operation is provided to simplify boot-up

synchronization among multiple processors sharing

the same bus.

80960CF-33 Datasheet(PDF) 48 Page - Intel Corporation

80960CF-33 Datasheet(HTML) 48 Page - Intel Corporation

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