80960SA datasheet(14/39 Pages) INTEL

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80960SA

Table 4. 80960SA Pin Description: Support Signals

NAME

TYPE

DESCRIPTION

RESET

RESET clears the processor’s internal logic and causes it to reinitialize.

During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3,

LOCK), the three-state output pins are placed in a HIGH impedance state (except

for DT/R, DEN, and AS) and other output pins are placed in their non-asserted

states.

RESET must be asserted for at least 41 CLK2 cycles for a predictable reset.

Optionally, for a synchronous reset, the LOW and HIGH transition of RESET

should occur after the rising edge of both CLK2 and the external bus CLK and

before the next rising edge of CLK2.

The interrupt pins indicate the initialization sequence executed. Typical initial-

ization requires driving only INT0 and INT3 to a HIGH state. The reset conditions

follow:

INT0

INT1

INT3

LOCK

Action Taken

Run self test (core initialization)

Disable self-test

Reserved

ONCE mode (see LOCK pin)

INT0

INTERRUPT 0 indicates a pending interrupt. To signal an interrupt in a

synchronous system, this pin — as well as the other interrupt pins — must be

enabled by being deasserted for at least one bus cycle and then asserted for at

least one additional bus cycle. In an asynchronous system, the pin must remain

deasserted for at least two system clock cycles and then asserted for at least two

more system clock cycles. The interrupt control register must be programmed with

an interrupt vector before using this pin.

INT0 is sampled during reset to determine if the self-test sequence is to be

executed.

INT1

INTERRUPT 1, like INT0, provides direct interrupt signaling. INT1 is sampled

during reset to determine if the self-test sequence is to be executed.

INT2/INTR

INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines

how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and

INT1 pins. If INTR, it is used to receive an interrupt request from an external

interrupt controller.

INT3/INTA

I/O

T.S.

INTERRUPT3/INTERRUPT ACKNOWLEDGE: The interrupt control register

determines how this pin is interpreted. If INT3, it has the same interpretation as

the INT0 and INT1 pins. If INTA, it is used as an output to control interrupt

acknowledge transactions. The INTA output is latched on-chip and remains valid

during Td cycles; as an output, it is open-drain. INT3 must be pulled HIGH during

reset.

N/A

NOT CONNECTED indicates pins should not be connected. Never connect any

pin marked NC; these pins may be reserved for factory use.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

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