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80960SA Datasheet(PDF) 23 Page - Intel Corporation |
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80960SA Datasheet(HTML) 23 Page - Intel Corporation |
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23 / 39 page ![]() 19 80960SA Figure 12. Processor Clock Pulse (CLK2) Figure 13. RESET Signal Timing HIGH LEVEL (MIN) 0.7VCC LOW LEVEL (MAX) 0.8V T1 T3 T5 T4 T2 90% 10% 1.5 V CLK2 CLK RESET OUTPUTS A B C D A B C T15 T16 INT0, INT1, INT3, LOCK INITIALIZATION PARAMETERS T17 NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 “A” edge. |
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