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82371SB Datasheet(PDF) 25 Page - Intel Corporation |
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82371SB Datasheet(HTML) 25 Page - Intel Corporation |
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25 / 122 page ![]() E 82371FB (PIIX) AND 82371SB (PIIX3) 25 Configuration Offset Mnemonic Register Register Access ACh CTLTMR Clock Scale STPCLK# Low Timer R/W ADh — Reserved — AEh CTHTMR Clock Scale STPCLK# High Timer R/W AF–FFh — Reserved — Table 3. PCI Configuration Registers—Function 1 (IDE Interface) Configuration Offset Mnemonic Register Register Access 00–01h VID Vendor Identification RO 02–03h DID Device Identification RO 04–05h PCICMD Command R/W 06–07h PCISTS PCI Device Status R/WC 08h RID Revision Identification RO 09 −0Bh CLASSC Class Code RO 0Ch — Reserved — 0Dh MLT Master Latency Timer R/W 0Eh HEDT Header Type RO 0F–1Fh — Reserved — 20–23h BMIBA Bus Master Interface Base Address R/W 24–3Fh — Reserved — 40–43h IDETIM IDE Timing Modes R/W 44h — Reserved (PIIX) — SIDETIM Slave IDE Timing Modes (PIIX3) R/W 45–FFh — Reserved — |
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