82371SB datasheet(67/122 Pages) INTEL

67 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

coded decimal (BCD) format. After writing the control word, a new count can be written at any time. The new

value takes effect according to the programmed mode.

Bit

Description

7:6

Counter Select. The Read Back Command is selected when bits[7:6] are both 1.

Bit[7:6]

Function

Counter 0 select

Counter 1 select

Counter 2 select

Read Back Command

5:4

Read/Write Select. The Counter Latch Command is selected when bits[5:4] are both 0.

Bit[5:4]

Function

Counter Latch Command

R/W Least Significant Byte

R/W Most Significant Byte

R/W LSB then MSB

3:1

Counter Mode Selection. Bits [3:1] select one of six possible counter modes.

Bit[3:1]

Mode

Function

000

Out signal on end of count (=0)

001

Hardware retriggerable one-shot

X10

Rate generator (divide by n counter)

X11

Square wave output

100

Software triggered strobe

101

Hardware triggered strobe

Binary/BCD Countdown Select. 0=Binary countdown. The largest possible binary count is

216. 1=Bbinary coded decimal (BCD) count is used. The largest BCD count allowed is 104.

Read Back Command

The Read Back Command is used to determine the count value, programmed mode, and current states of the

OUT pin and Null count flag of the selected counter or counters. The Read Back Command is written to the

Timer Control Word Register which latches the current states of the above mentioned variables. The value of

the counter and its status may then be read by I/O access to the counter address. Note that The Timer

Counter Register bit definitions are different during the Read Back Command than for a normal Timer

Counter Register write.

Bit

Description

7:6

Read Back Command. When bits[7:6]=11, the Read Back Command is selected during a

write to the Timer Control Word Register. Following the Read Back Command, I/O reads from

the selected counter’s I/O addresses produce the current latch status, the current latched

count, or both if bits 4 and 5 are both 0.

Latch Count of Selected Counters. When bit 5=0, the current count value of the selected

counters will be latched. When bit 5=1, the count will not be latched.

Latch Status of Selected Counters. When bit 4=0, the status of the selected counters will be

latched. When bit 4=1, the status will not be latched. The status byte format is described in

Section 4.3.3, Interval Timer Status Byte Format Register.

82371SB Datasheet(PDF) 67 Page - Intel Corporation

82371SB Datasheet(HTML) 67 Page - Intel Corporation

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