82371SB datasheet(59/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.4.14.

LEGSUP

LEGACY SUPPORT REGISTER (FUNCTION 2) (PIIX3)

PCI Address Offset:

−C1h

Default:

2000h

Attribute:

Read/Write Clear

This register provides control and status capability for the legacy keyboard and mouse functions.

Bit

Description

End OF A20GATE Pass-through Status (A20PTS)

R/WC. This bit is set to 1 to indicate

that the A20GATE pass-through sequence has ended. Software must use the enable bits to

determine the exact cause of an SMI#. Software cleats this bit by writing a 1 to it.

Reserved.

USB PIRQ Enable (USBPIRQDEN)

R/W. 1=USB interrupt is routed to PIRQD (default).

0=USB interrupt does not route to PIRQD. This bit prevents the USB controller from generating

an interrupt. Note that PIIX3 will typically be configured to generate an SMI using bit 4 of this

USB IRQ Status (USBIRQS)

RO. PIIX3 sets this bit to 1 to indicate that the USB IRQ is

active. Software must use the enable bits to determine the exact cause of an SMI#. Writing a

1 to this bit will have no effect. Software must clear the IRQ via the USB controller.

Trap By 64h Write Status (TBY64W)

R/WC. PIIX3 sets this bit to 1 to indicate that a write

to port 64h occurred. Software must use the enable bits to determine the exact cause of an

SMI#. Software clears this bit by writing a 1 to it.

Trap By 64h Read Status (TBY64R)

R/WC. PIIX3 sets this bit to 1 to indicate that a read to

port 64h occurred. Software must use the enable bits to determine the exact cause of an

SMI#. Software clears this bit by writing a 1 to it.

Trap By 60h Write Status (TBY60W)

R/WC. PIIX3 sets this bit to 1 to indicate that a write

to port 60h occurred. Software must use the enable bits to determine the exact cause of an

SMI#. Software clears this bit by writing a 1 to it.

Trap By 60h Read Status (TBY60R)

R/WC. PIIX3 sets this bit to 1 to indicate that a read to

port 60h occurred. Software must use the enable bits to determine the exact cause of an

SMI#. Software clears this bit by writing a 1 to it.

SMI At End Of Pass-through Enable (SMIEPTE)

R/W. 1=Enable the generation of an SMI

when the A20GATE pass-through sequence has ended. 0=Disable (default). This may be

required if an SMI is generated by a USB interrupt in the middle of an A20GATE pass-through

sequence and needs to be serviced later.

Pass-through Status (PSS)

RO. 1=A20GATE pass-through sequence is currently in

progress. 0=Not currently executing the A20GATE pass-through sequence (default). This bit

indicates that the host controller is executing the A20GATE pass-through sequence. If

software needs to reset this bit, it should set Bit 5 to 0 causing the host controller to

immediately end the A20GATE pass-through sequence.

82371SB Datasheet(PDF) 59 Page - Intel Corporation

82371SB Datasheet(HTML) 59 Page - Intel Corporation

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