82371SB datasheet(34/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

increase the delay in increments of SYSCLKs. No additional delay is inserted for back-to-back I/O "sub

cycles" generated as a result of byte assembly or disassembly. This register defaults to 8 and 16-bit recovery

enabled with one SYSCLK clock added to the standard I/O recovery.

Bit

Description

DMA Reserved Page Register Aliasing Control (DMAAC). When DMAAC=0, the PIIX/PIIX3

aliases I/O accesses in the 90–9Fh range to the 80–8Fh range. In this case, the PIIX/PIIX3

only forwards write accesses to these locations to the ISA Bus.

PIIX: When DMAAC=1, the PIIX disables aliasing for the following registers; 80h, 84

−86h, 88h,

and 8C

−8Eh. When disabled, the PIIX forwards read and write accesses to these registers to

the ISA.

PIIX3: When DMAAC=1, the PIIX3 disables aliasing for the entire 90–9Fh range (they are

considered ISA bus register locations). When disabled, the PIIX3 forwards read ands write

accesses to these registers to ISA.

Note, that port 92h is always a distinct ISA register in the 90–9Fh range and is always

forwarded to the ISA Bus. When DMAAC=1, ISA master accesses to the 90–9Fh range are

ignored by the PIIX. Also, when DMAAC=1, the PIIX/PIIX3 does not re-load the power

management fast-off-timer with its original value for accesses to the 90–9Fh address range.

8-Bit I/O Recovery Enable. 1=Enable the recovery time programmed in bits [5:3]. 0=Disable

recovery times in bits [5:3] and the recovery timing of 3.5 SYSCLKs is inserted.

5:3

8-Bit I/O Recovery times. When bit 6=1, this 3-bit field defines the recovery time for 8-bit I/O.

Bit[5:3]

SYSCLK

Bit[5:3]

SYSCLK

001

101

010

110

011

111

100

000

16-Bit I/O Recovery Enable. 1=Enable, the recovery times programmed in bits [1:0].

0=Disable, programmable recovery times in bits [1:0] and the recovery timing of 3.5 SYSCLKs

is inserted.

1:0

16-Bit I/O Recovery Times. When bit 2=1, this 2-bit defines the recovery time for 16-bit I/O.

Bit[1:0]

SYSCLK

2.2.9.

XBCS—X-BUS CHIP SELECT REGISTER (Function 0)

Address Offset:

4Eh (PIIX)

−4Fh (PIIX3)

Default Value:

03h

Attribute:

Read/Write

This register enables/disables accesses to the RTC, keyboard controller, IOAPIC (PIIX3 only), and BIOS.

Disabling any of these bits prevents the chip select and X-Bus output enable control signal (XOE#) for that

device from being generated. This register also provides coprocessor error and mouse functions.

82371SB Datasheet(PDF) 34 Page - Intel Corporation

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