W78IRD2 datasheet(46/76 Pages) ETC2

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W78IRD2

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CMOD(D8H): PCA counter mode register

BIT

NAME

FUNCTION

CILD

Counter idle control: CILD = 0 programs the PCA Counter to continue functioning

in idle mode; CILD = 1 programs it to stop in idle mode.

WDTE

Watchdog Timer Enable: WDTE = 0 disables the Watchdog Timer function in

PCA module 4. WDTE = 1 enables it.

Reserved

CPS1

PCA Count Pulse Select bit 1

CPS0

PCA Count Pulse Select bit 0

ECF

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to

generate an interrupt. ECF = 0 disables the interrupt.

There are three additional bits in the CMOD SFR. CILD allows the PCA to stop during idle mode,

WDTE enables and disables the watchdog function executed in module 4, and ECF causes an

interrupt when the PCA timer overflows (and the PCA overflow flag CF is set).

The CCON SFR contains the run-control bit for the PCA and the flags for the PCA timer overflow (CF)

and each module match / capture (CCFn).

CCON(D8H): PCA counter control register

BIT

NAME

FUNCTION

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF

generates an interrupt if bit ECF in CMOD is set. CF may be set by either

hardware or software but can only be cleared by software.

PCA Counter Run control bit. Set by software to turn on the PCA counter. Must be

cleared by software to turn the PCA counter off.

Reserved

CCF4

PCA Module4 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF3

PCA Module3 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF2

PCA Module2 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF1

PCA Module1 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF0

PCA Module0 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

The CR bit (CCON.6) must be set by the software, and the PCA is turned off by clearing this bit. The

CF bit (CCON.7) is set when the PCA Counter overflows, and an interrupt is generated if the ECF bit in

the CMOD register is set. The CF bit can only be cleared by software. CCON.0~CCON.4 are the flags

for the modules and are set by hardware when either a match or a capture occurs. These flags can

only be cleared by software.

The next five sections provide more information about each of the five modes (four modes for all

registers and the watchdog timer in module 4).

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