AD7650 datasheet(4/20 Pages) AD

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REV. 0

AD7650

–4–

TIMING SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

REFER TO FIGURES 13 AND 14 (continued)

SCLK Last Edge to SYNC Delay

t24

CS HIGH to SYNC HI-Z

t25

CS HIGH to Internal SCLK HI-Z

t26

CS HIGH to SDOUT HI-Z

t27

BUSY HIGH in Master Serial Read After Convert

t28

2.75/3/3.25

µs

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to SYNC Asserted Delay

t29

1/1.25/1.5

µs

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Deasserted to BUSY LOW Delay

t30

REFER TO FIGURES 15 AND 16

(Slave Serial Interface Modes)

External SCLK Setup Time

t31

5ns

External SCLK Active Edge to SDOUT Delay

t32

316

SDIN Setup Time

t33

5ns

SDIN Hold Time

t34

5ns

External SCLK Period

t35

External SCLK HIGH

t36

External SCLK LOW

t37

NOTES

1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C

L of 10 pF; otherwise, the load is 60 pF maximum.

3If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.

Specifications subject to change without notice.

(continued)

IOH

500 A

1.6mA

IOL

TO OUTPUT

1.4V

60pF*

*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

Figure 1. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, SCLK Outputs, CL = 10 pF

0.8V

DELAY

Figure 2. Voltage Reference Levels for Timing

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