AD7650 datasheet(13/20 Pages) AD

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AD7650

POWER DISSIPATION VS. THROUGHPUT

Operating currents are very low during the acquisition phase,

which allows a significant power saving when the conversion

rate is reduced as shown in Figure 7. This power saving depends

on the mode used. In impulse mode, the AD7650 automatically

reduces its power consumption at the end of each conversion

phase. This feature makes the AD7650 ideal for very low power

battery applications. It should be noted that the digital interface

remains active even during the acquisition phase. To reduce the

operating digital supply currents even further, the digital inputs

need to be driven close to the power supply rails (i.e., DVDD or

DGND for all inputs except EXT/

INT, INVSYNC, INVSCLK,

RDC/SDIN, and OVDD or OGND for these last four inputs).

100k

0.1

SAMPLING RATE – SPS

100k

100

10k

100

0.1

WARP/NORMAL

IMPULSE

Figure 7. Power Dissipation vs. Sampling Rate

CONVERSION CONTROL

Figure 8 shows the detailed timing diagrams of the conversion

process. The AD7650 is controlled by the signal

CNVST which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The

CNVST signal operates independently of

CS and RD signals.

CNVST

BUSY

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

Figure 8. Basic Conversion Timing

In impulse mode, conversions can be automatically initiated.

CNVST is held low when BUSY is low, the AD7650 controls

the acquisition phase and then automatically initiates a new

conversion. By keeping

CNVST low, the AD7650 keeps the

conversion process running by itself. It should be noted that the

analog input has to be settled when BUSY goes low. Also, at

power-up,

CNVST should be brought low once to initiate the

conversion process. In this mode, the AD7650 could sometimes

run slightly faster then the guaranteed limits in the impulse mode

of 444 kSPS. This feature does not exist in warp or normal modes.

RESET

DATA

BUSY

CNVST

Figure 9. RESET Timing

Although

CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

It is a good thing to shield the

CNVST trace with ground and

also to add a low value serial resistor (i.e., 50 V) termination

close to the output of the component that drives this line.

For applications where the SNR is critical,

CNVST signal should

have a very low jitter. Some solutions to achieve that is to use a

dedicated oscillator for

CNVST generation or, at least, to clock

it with a high-frequency low-jitter clock as shown in Figure 5.

DIGITAL INTERFACE

The AD7650 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7650 digital interface also accommodates both 3 V or 5 V logic

by simply connecting the OVDD supply pin of the AD7650 to

the host system interface digital supply. Finally, by using the

OB/

2C input pin, both two’s complement or straight binary

coding can be used.

The two signals

CS and RD control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually,

CS allows the selection of each AD7650 in

multicircuits applications and is held low in a single AD7650

design.

RD is generally used to enable the conversion result on

the data bus.

t11

CNVST

BUSY

DATA

BUS

CS = RD = 0

t10

PREVIOUS CONVERSION DATA

NEW DATA

Figure 10. Master Parallel Data Timing for Reading

(Continuous Read)

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