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CD4536BMS Datasheet(PDF) 12 Page - Intersil Corporation

Part # CD4536BMS
Description  CMOS Programmable Timer
PDF  13 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4536BMS Datasheet(HTML) 12 Page - Intersil Corporation

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7-1247
CD4536BMS
FIGURE 22. TIME INTERVAL CONFIGURATION USING ON-
CHIP RC OSCILLATOR AND RESET INPUT
TO INITIATE TIME INTERVAL
FIGURE 23. TIMING DIAGRAM
DECODE OUT SELECTION TABLE
DCBA
NUMBER OF STAGES IN DIVIDER CHAIN
8-BYPASS = 0
8-BYPASS = 1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
9
10
11
12
1
2
3
4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
13
14
15
16
5
6
7
8
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
17
18
19
20
9
10
11
12
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
21
22
23
24
13
14
15
16
0 = Low Level
1 = High Level
Functional Block Diagram
FIGURE 24.
Applications (Continued)
A
B
C
D
8-BYPASS
OSC INH
C INH
SET
RESET
MONO IN
OUT 1
OUT 2
DECODE
OUT
IN 1
VDD
t
RS
Rtc
C
VSS
START
f
≅
1
2.3
Rtc C
RS
≥ 2Rtc
f IN Hz,
R IN
Ω,
C IN F
NOTE:
SHADED PULSE REPRESENTS DECODE OUTPUT
IN MONOSTABLE MODE. IF AN OUTPUT PULSE
IS REQUIRED 1 FULL COUNTDOWN AFTER
REMOVAL OF RESET PULSE, SEE FIGURE 19
FOR USE OF CD4098BMS
R
CLOCK
DCBA
0000 (
÷2)
0001 (
÷4)
0010 (
÷8)
3
µs MIN
VSS = 8
VDD = 16
9
10
11
12
15
A
B
C
D
BINARY
SELECT
MONO IN
13 DECODE
OUT
DECODER
STAGES 9-24
Q9 - - - Q24
CLOCK INHIBIT
LOGIC
STAGES
1-8
8-BYPASS
LOGIC
OSC INHIBIT
LOGIC
IN
3
RESET
2
SET
1
OSC 14
INHIBIT
OUT 1
4
OUT 2
5
CLOCK 7
INHIBIT
8-BYPASS
6



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