28

#2

7

F

DSBI

DECIMAL ADJUST

→ DF, D

HIGH Z

RP + 1

1

1

0

S1#1

8

0-F

SCAL

RN.0, RN.1

→ T, B

HIGH Z

RN

1

1

0

#2

8

0-F

SCAL

T

→ MRX RX - 1 → RX

RN.0

RX

1

0

0

#3

8

0-F

SCAL

B

→ MRX RX - 1 → RX

RN.1

RX - 1

1

0

0

#4

8

0-F

SCAL

RP.0, RP.1

→ T, B

HIGH Z

RP

1

1

0

#5

8

0-F

SCAL

B, T

→ RN.1, RN.0

HIGH Z

RN

1

1

0

#6

8

0-F

SCAL

MRN

→ B; RN + 1 → RN

MRP

RP

0

1

0

#7

8

0-F

SCAL

B

→ T; MRN → B; RN + 1 → RN M(RP + 1)

RP + 1

0

1

0

#8

8

0-F

SCAL

B, T

→ RP.0, RP.1

HIGH Z

RP

1

1

0

S1#1

9

0-F

SRET

RN.0, RN.1

→ T, B

HIGH Z

RN

1

1

0

#2

9

0-F

SRET

RX + 1

→ RX

HIGH Z

RX

1

1

0

#3

9

0-F

SRET

B, T

→ RP.1, RP.0

HIGH Z

RP

1

1

0

#4

9

0-F

SRET

MRX

→ B; RX + 1 → RX

M(RX + 1)

RX + 1

0

1

0

#5

9

0-F

SRET

B

→ T; MRX → B

M(RX + 1

RX + 2

0

1

0

#6

9

0-F

SRET

B, T

→ RN.0, RN.1

HIGH Z

RN

1

1

0

S1#1

A

0-F

RSXD

RN.0, RN.1

→ T, B

HIGH Z

RN

1

1

0

#2

A

0-F

RSXD

T

→ MRX; RX - 1 → RX

RN.0

RX

1

0

0

#3

A

0-F

RSXD

B

→ MRX; RX - 1 → RX

RN.1

RX - 1

1

0

0

S1#1

B

0-F

RNX

RN.0, RN.1

→ T, B

HIGH Z

RN

1

1

0

#2

B

0-F

RNX

B, T

→ RX.1, RX.0

HIGH Z

RX

1

1

0

S1#1

C

0-F

RLDI

MRP

→ B; RP + 1 → RP

MRP

RP

0

1

0

#2

C

0-F

RLDI

B

→ T; MRP → B; RP + 1 → RP

M(RP + 1)

RP + 1

0

1

0

#3

C

0-F

RLDI

B, T

→ RN.0, RN.1;`

RP + 1

→ RP

HIGH Z

RN

1

1

0

S1#1

F

4

DADD

MRX + D

→ DF; D

MRX

RX

0

1

0

#2

F

4

DADD

DECIMAL ADJUST

→ DF, D

HIGH Z

RP

1

1

0

S1#1

F

7

DSM

D - MRX

→ DF, D

MRX

RX

0

1

0

#2

F

7

DSM

DECIMAL ADJUST

→ DF, D

HIGH Z

RP

1

1

0

S1#1

F

C

DADI

MRP + D

→ DF, D;

RP + 1

→ RP

MRP

RP

0

1

0

#2

F

C

DADI

DECIMAL ADJUST

→ DF, D

HIGH Z

RP + 1

1

1

0

S1#1

F

F

DSMI

D - MRP

→ DF, D

RP + 1

→ RP

MRP

RP

0

1

0

#2

F

F

DSMI

DECIMAL ADJUST

→ DF, D

HIGH Z

RP + 1

1

1

0

NOTE:

20. Data bus floats for first 2-1/2 clocks of the nine clock initialization cycle; all zeros for remainder of cycle.

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

STATE

I

N

MNEMONIC

OPERATION

DATA

BUS

MEMORY

ADDRESS

MRD

MWR

N

LINES

CDP1805AC, CDP1806AC