HC5526IP datasheet(14/18 Pages) INTERSIL

14 / 18 page

SLIC Operating States

Power-Up Sequence

The HC5526 has no required power-up sequence. This is a

result of the Dielectrically Isolated (DI) process used in the

fabrication of the part. By using the DI process, care is no

longer required to insure that the substrate be kept at the

most negative potential as with junction isolated ICs.

Printed Circuit Board Layout

Care in the printed circuit board layout is essential for proper

operation. All connections to the RSN pin should be made as

close to the device pin as possible, to limit the interference

that might be injected into the RSN terminal. It is good

practice to surround the RSN pin with a ground plane.

The analog and digital grounds should be tied together at

the device.

Notes

2. Overload Level (Two-Wire port). The overload level is speciﬁed

at the 2-wire port (VTR0) with the signal source at the 4-wire

receive port (ERX). IDCMET = 30mA, increase the amplitude of

ERX until 1% THD is measured at VTRO. Reference Figure 1.

3. Longitudinal Impedance. The longitudinal impedance is com-

puted using the following equations, where TIP and RING volt-

ages are referenced to ground. LZT,LZR,VT,VR,AR and AT

are deﬁned in Figure 2.

(TIP) LZT = VT/AT,

(RING) LZR = VR/AR,

where: EL = 1VRMS (0Hz to 100Hz).

4. Longitudinal Current Limit (Off-Hook Active). Off - Hook

(Ac-

tive, C1 =1,C2 = 0) longitudinal current limit is determined by

increasing the amplitude of EL (Figure 3A) until the 2-wire

longitudinal balance drops below 45dB. DET pin remains low

(no false detection).

5. Longitudinal Current Limit (On-Hook Standby). On - Hook

(Active, C1 =1,C2 = 1) longitudinal current limit is determined

by increasing the amplitude of EL (Figure 3B) until the 2-wire

longitudinal balance drops below 45dB. DET pin remains high

(no false detection).

6. Longitudinal to Metallic Balance. The longitudinal to metallic

balance is computed using the following equation:

BLME = 20

• log (EL/VTR), where: EL and VTR are deﬁned in

Figure 4.

7. Metallic to Longitudinal FCC Part 68, Para 68.310. The

metallic to longitudinal balance is defined in this spec.

8. Longitudinal to Four-Wire Balance. The longitudinal to 4-wire

balance is computed using the following equation:

BLFE = 20

• log (EL/VTX),: EL and VTX are deﬁned in Figure 4.

9. Metallic to Longitudinal Balance. The metallic to longitudinal

balance is computed using the following equation:

BMLE = 20

• log (ETR/VL), ERX = 0,

where: ETR,VL and ERX are deﬁned in Figure 5.

10. Four-Wire to Longitudinal Balance. The 4-wire to longitudinal

balance is computed using the following equation:

BFLE = 20

• log (ERX/VL), ETR = source is removed,

where: ERX,VL and ETR are deﬁned in Figure 5.

TABLE 1. LOGIC TRUTH TABLE

SLIC OPERATING STATE

ACTIVE DETECTOR

DET OUTPUT

0000

Open Circuit

No Active Detector

Logic Level High

0001

Active

Ground Key Detector

Ground Key Status

0010

Ringing

No Active Detector

Logic Level High

0011

Standby

Ground Key Detector

Ground Key Status

0100

Open Circuit

No Active Detector

Logic Level High

0101

Active

Loop Current Detector

Loop Current Status

0110

Ringing

Ring Trip Detector

Ring Trip Status

0111

Standby

Loop Current Detector

Loop Current Status

1000

Open Circuit

No Active Detector

Logic Level High

1001

Active

Ground Key Detector

1010

Ringing

No Active Detector

1011

Standby

Ground Key Detector

1100

Open Circuit

No Active Detector

1101

Active

Loop Current Detector

1110

Ringing

Ring Trip Detector

1111

Standby

Loop Current Detector

HC5526

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