AD9834 datasheet(6/32 Pages) AD

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AD9834

Data Sheet

TIMING CHARACTERISTICS

DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.

Table 2.

Parameter1

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

20/13.33

ns min

MCLK period: 50 MHz/75 MHz

8/6

ns min

MCLK high duration: 50 MHz/75 MHz

8/6

ns min

MCLK low duration: 50 MHz/75 MHz

ns min

SCLK period

ns min

SCLK high duration

ns min

SCLK low duration

ns min

FSYNC-to-SCLK falling edge setup time

t8 MIN

ns min

FSYNC-to-SCLK hold time

t8 MAX

t4 − 5

ns max

ns min

Data setup time

t10

ns min

Data hold time

t11

ns min

FSELECT, PSELECT setup time before MCLK rising edge

t11A

ns min

FSELECT, PSELECT setup time after MCLK rising edge

t12

ns min

SCLK high to FSYNC falling edge setup time

Guaranteed by design, not production tested.

Timing Diagrams

MCLK

Figure 3. Master Clock

FSELECT,

PSELECT

VALID DATA

MCLK

t11A

t11

Figure 4. Control Timing

SCLK

FSYNC

SDATA

D15

D14

D15

D14

t12

t10

Figure 5. Serial Timing

Rev. D | Page 6 of 32

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