AD14060L datasheet(39/48 Pages) AD

39 / 48 page

AD14060/AD14060L

Rev. B | Page 39 of 48

Multiprocessor EPROM Booting

The following methods boot the multiprocessor system from an

EPROM:

• SHARC_A is booted, which then boots the others.

The EBOOT pin on the SHARC_A must be set high for

EPROM booting. All other ADSP-21060s should be

configured for host booting (EBOOT = 0, LBOOT = 0, and

BMS = 1), which leaves them in the idle state at startup and

allows SHARC_A to become bus master and boot itself.

Only the BMS pin of SHARC_A is connected to the chip

select of the EPROM. When SHARC_A has finished

booting, it can boot the remaining ADSP-21060s by writing

to their external port DMA Buffer 0 (EPB0) via multiproc-

essor memory space.

• All ADSP-21060s boot in turn from a single EPROM.

The BMS signals from each ADSP-21060 can be wire-OR’ed

together to drive the chip select pin of the EPROM. Each

ADSP-21060 can boot in turn, according to its priority.

When the last one has finished booting, it must inform the

others (which can be in the idle state) that program

execution can begin.

Multiprocessor Link-Port Booting

Booting can also be accomplished from a single source through

the link ports. Link Buffer 4 must always be used for booting. To

simultaneously boot all the ADSP-21060s, a parallel common

connection is available through Link Port 4 on each of the

processors. Or, using the daisy-chain connection that exists

between the processors’ link ports, each ADSP-21060 can boot

the next one in turn. In this case, the link assignment register

(LAR) must be programmed to configure the internal link ports

with Link Buffer 4.

Multiprocessor Booting from External Memory

If external memory contains a program after reset, then

SHARC_A should be set up for no-boot mode. It begins execut-

ing from Address 0x0040 0004 in external memory. When

booting has completed, the other ADSP-21060s can be booted

by SHARC_A, if they are set up for host booting; or they can

begin executing out of external memory, if they are set up for

no-boot mode. Multiprocessor bus arbitration allows this

booting to occur in an orderly manner.

HOST PROCESSOR INTERFACE

The AD14060/AD14060L’s host interface allows easy connec-

tion to standard microprocessor buses, both 16-bit and 32-bit,

with little additional hardware required. Asynchronous transfers

at speeds of up to the full clock rate of the module are sup-

ported. The host interface is accessed through the AD14060/

AD14060L external port and is memory-mapped into the

unified address space. Four channels of DMA are available for

the host interface; code and data transfers are accomplished

with low software overhead.

The host processor requests the AD14060/AD14060L’s external

bus with the host bus request (HBR), host bus grant (HBG), and

ready (REDY) signals. The host can directly read and write the

internal memory of the SHARCs, and can access the DMA

channel setup and mailbox registers. Vector interrupt support is

provided for efficient execution of host commands.

DIRECT MEMORY ACCESS (DMA) CONTROLLER

The SHARCs’ on-chip DMA control logic allows zero-overhead

data transfers without processor intervention. The DMA

controller operates independently and invisibly to each

SHARC’s processor core, allowing DMA operations to occur

while the core is simultaneously executing its program

instructions.

DMA transfers can occur between SHARC internal memory

and either external memory, external peripherals, or a host

processor. DMA transfers can also occur between the SHARC’s

internal memory and its serial ports or link ports. DMA

transfers between external memory and external peripheral

devices are another option. External bus packing to 16-, 32- or

48-bit words is performed during DMA transfers.

Ten channels of DMA are available on the SHARCs: two via the

link ports, four via the serial ports, and four via the processor’s

external port (for either host processor, other SHARCs,

memory, or I/O transfers). Four additional link port DMA

channels are shared with Serial Port 1 and the external port.

Programs can be downloaded to the SHARCs using DMA

transfers. Asynchronous off-module peripherals can control two

DMA channels using DMA request/grant lines (DMAR1-2,

DMAG1-2). Other DMA features include interrupt generation

upon completion of DMA transfers and DMA chaining for

automatic linked DMA transfers.

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